Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs

摘要

In this paper,we present Generic System Verilog Universal VerificationMethodology based Reusable Verification Environment for efficient verificationof Image Signal Processing IP's/SoC's. With the tight schedules on all projectsit is important to have a strong verification methodology which contributes toFirst Silicon Success. Deploy methodologies which enforce full functionalcoverage and verification of corner cases through pseudo random test scenariosis required. Also, standardization of verification flow is needed. Previously,inside imaging group of ST, Specman (e)/Verilog based Verification Environmentfor IP/Subsystem level verification and C/C++/Verilog based DirectedVerification Environment for SoC Level Verification was used for FunctionalVerification. Different Verification Environments were used at IP level and SoClevel. Different Verification/Validation Methodologies were used for SoCVerification across multiple sites. Verification teams were also looking forthe ways how to catch bugs early in the design cycle? Thus, Generic SystemVerilog Universal Verification Methodology (UVM) based Reusable VerificationEnvironment is required to avoid the problem of having so many methodologiesand provides a standard unified solution which compiles on all tools. The mainaim of development of this Generic and automatic verification environment is todevelop an efficient and unified verification environment (at IP/Subsystem/SoCLevel) which reuses the already developed Verification components and alsosequences written at IP/Subsystem level can be reused at SoC Level both withHost BFM and actual Core using Incisive Software Extension (ISX) and VirtualRegister Interface (VRI)/Verification Abstraction Layer (VAL) approaches.IP-XACT based tools are used for automatically configuring the environment forvarious imaging IPs/SoCs.